A CAD Tool of Adaptive Coverage Exclusions for Complex Industrial HDL Designs

Functional simulation is still the primary workhorse for verifying the correctness of hardware designs. Code coverage is a key contributor to any verification process, as it is strongly correlated to test-bench quality metering and effectiveness of the whole verification flow. It also measures the extent of design verification provided by a set of functional simulation vectors which should compute the statement execution counts (controllability information). Code coverage exclusion has always been associated with the verification process to have reasonable coverage results and for the purpose of debugging a particular segment of the design. Keeping tracing of the excluded parts along with the frequent editing has become a hurdle to a lot of designers. In this paper, we present a novel adaptive exclusion methodology based on source code annotation. This tool acts as a third-party tool that works side by side with any functional simulation tool. Furthermore, the reliability of the tool for any source modifications and its performance overhead were evaluated empirically through extensive simulations over very large industrial projects, showing that the average execution time overhead for 10 million lines of code project is on average 0.4% only.