A. Vandooren, A. Alian, A. Verhulst, J. Franco, R. Rooyackers, Q. Smets, D. Verreck, N. Waldron, D. Mocuta, N. Collaert
{"title":"用于低功率电子器件的隧道场效应管","authors":"A. Vandooren, A. Alian, A. Verhulst, J. Franco, R. Rooyackers, Q. Smets, D. Verreck, N. Waldron, D. Mocuta, N. Collaert","doi":"10.1109/S3S.2016.7804386","DOIUrl":null,"url":null,"abstract":"We report on Tunnel Field-Effect Transistors for low power electronics. Thanks to their potential to reach sub-60mV/dec subthreshold slope, these devices are very attractive for use in circuits with sub-0.5V supply voltage. However, proper device design as well as material choice is not obvious and many implementations have shown larger slope than expected, due to parasitic trap-assisted tunneling conduction. We review work done at imec on tunnelFETs. Initial work was based on vertical nanowire structures using goup-IV semiconductor materials. More recently, implementation of TunnelFETS on III-V materials using a Zn-diffusion approach for source doping was demonstrated with an attractive slope below 60mV/dec. Trap-assisted tunneling is extracted from the devices characteristics based on the activation energy of different conduction mechanisms present in the devices.","PeriodicalId":145660,"journal":{"name":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Tunnel FETs for low power electronics\",\"authors\":\"A. Vandooren, A. Alian, A. Verhulst, J. Franco, R. Rooyackers, Q. Smets, D. Verreck, N. Waldron, D. Mocuta, N. Collaert\",\"doi\":\"10.1109/S3S.2016.7804386\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report on Tunnel Field-Effect Transistors for low power electronics. Thanks to their potential to reach sub-60mV/dec subthreshold slope, these devices are very attractive for use in circuits with sub-0.5V supply voltage. However, proper device design as well as material choice is not obvious and many implementations have shown larger slope than expected, due to parasitic trap-assisted tunneling conduction. We review work done at imec on tunnelFETs. Initial work was based on vertical nanowire structures using goup-IV semiconductor materials. More recently, implementation of TunnelFETS on III-V materials using a Zn-diffusion approach for source doping was demonstrated with an attractive slope below 60mV/dec. Trap-assisted tunneling is extracted from the devices characteristics based on the activation energy of different conduction mechanisms present in the devices.\",\"PeriodicalId\":145660,\"journal\":{\"name\":\"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/S3S.2016.7804386\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/S3S.2016.7804386","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We report on Tunnel Field-Effect Transistors for low power electronics. Thanks to their potential to reach sub-60mV/dec subthreshold slope, these devices are very attractive for use in circuits with sub-0.5V supply voltage. However, proper device design as well as material choice is not obvious and many implementations have shown larger slope than expected, due to parasitic trap-assisted tunneling conduction. We review work done at imec on tunnelFETs. Initial work was based on vertical nanowire structures using goup-IV semiconductor materials. More recently, implementation of TunnelFETS on III-V materials using a Zn-diffusion approach for source doping was demonstrated with an attractive slope below 60mV/dec. Trap-assisted tunneling is extracted from the devices characteristics based on the activation energy of different conduction mechanisms present in the devices.