Compact inductors deembedded with asymmetric through-only structures

This paper investigates the use of asymmetric through-only de-embedding approach for on-chip stacked inductors. Silicon structures are fabricated on a standard 28nm CMOS process and characterized with a network analyzer on folded GSGSG pads to facilitate rapid, one-touch measurements. The proposed de-embedding approach is compared with the conventional de-embedding approach. Additionally, the proposed de-embedded inductance and quality factor values are compared with a conventional physics based model as well as electromagnetic simulations. Along with the simplicity of the de-embedding structure, one can expect reduced silicon real estate cost during testing and characterization of multiple layer stacked inductors. As a result, the response of compact stacked inductors can become increasingly predictable to accommodate the demand of decreasing costs for wireline and wireless interfaces while providing increasing circuit and system performance.