Package thermal resistance model dependency on equipment design

A physical model is presented that describes mechanisms for operating-equipment junction-to-ambient thermal resistance in excess of a typical component manufacturer's data-sheet value by as much as a factor of four under constant cooling conditions. The model accounts for the discrepancy between system thermal performance of a package and data-sheet thermal resistance value which are not accompanied by qualifying data in the form of junction-to-header thermal resistance, board temperature rise over ambient, convection coefficient, mounting sensitivity, and power dissipation. The eight constants used to predict inherent increases in package thermal resistance when going from the data-sheet-specified operating conditions to the excess-value conditions are described. These constants and procedures for obtaining them are given for dual in-line packages (DIPs), pin-grid arrays (PGAs), small-outline transistors (SOTs), and plastic leaded chip carriers (PLCCs).<>