High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator

This paper proposes a neural network accelerator for Tiny-Yolo V2. The data format of input feature maps, output feature maps, and weight kernels are converted to uint8 through a quantization strategy to reduce the data size and make the hardware utilization more efficient. Moreover, we propose an input feature maps placement method to reduce bandwidth utilization and improve PE utilization. To verify the hardware implementation, the Xilinx ZCU102 platform is used to verify the hardware architecture. Synthesis results show that the proposed architecture implements in 90nm can achieve 14.4GOPS@100Mhz with area efficiency by 99 GOPS/M-gates.