半导体元件系统级ESD测试的最佳实践

K. Muhonen
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引用次数: 2

摘要

集成电路(ic)的静电放电(ESD)测试是必要的,以确保产品能够承受多种类型的ESD威胁,包括在工厂和现场遇到的ESD威胁。本文讨论了静电应力波形对部件的测试,这种测试最初是为预测系统故障而设计的。IC制造商在对其组件进行系统测试时难以获得可靠的数据,因为这种形式的评估存在接口、实施和设备可重复性问题。本文强调了系统级ESD测试的最佳实践,尽管存在这些障碍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Best Practices for System Level ESD Testing of Semiconductor Components
Electrostatic discharge (ESD) testing of integrated circuits (ICs) is necessary to ensure products can withstand several types of ESD threats including those encountered in the factory and in the field. This paper discusses the testing of components with electrostatic stress waveforms that were originally designed for predicting system failures in the field. IC manufacturers are struggling to obtain reliable data when applying system tests to their components because of interface, implementation and equipment repeatability problems found with this form of evaluation. This paper highlights the best practices for system level ESD testing despite these hurdles.
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