13.3ns双精度浮点ALU和乘法器

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI:10.1109/ICCD.1995.528909

H. Yamada, T. Hotta, T. Nishiyama, F. Murabayashi, T. Yamauchi, H. Sawamoto

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引用次数: 21

摘要

针对浮点算术逻辑单元(ALU)，开发了对齐移位前的1位预移位、预期前导“1”位的归一化和预舍入技术。此外，还开发了浮点乘法器的进位选择、加法和预舍入技术。设计了一种容噪预充电路，并将其应用于ALU和乘法器。这些技术使关键路径的延迟时间减少了24%。每个单元采用0.3 /spl mu/m 2.5 V四层金属CMOS技术制造，并在150 MHz下实现了两周延迟。

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A 13.3ns double-precision floating-point ALU and multiplier

One-bit pre-shifting before alignment shift, normalization with anticipated leading '1' bit and pre-rounding techniques have been developed for a floating-point arithmetic logic unit (ALU). In addition, carry select addition and pre-rounding techniques have been developed for a floating-point multiplier. A noise tolerant precharge (NTP) circuit was designed and applied to the ALU and multiplier. These techniques reduced the delay time of the critical path by 24%. Each unit was fabricated in 0.3 /spl mu/m 2.5 V four-layer-metal CMOS technology and achieved a two-cycle latency at 150 MHz.

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Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors

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