{"title":"用于生物传感器SOC低功耗应用的嵌入式CMOS CR SAR ADC设计","authors":"Lungui Zhong, Haigang Yang, Chong Zhang","doi":"10.1109/ICASIC.2007.4415719","DOIUrl":null,"url":null,"abstract":"This paper presents a Charge Redistribution Successive Approximation Register ADC designed in a 0.35-mum standard CMOS process. The total power consumption is only 4.6 mW, and a resolution of 10 bits is achieved. The ADC maintains a maximum DNL of less than 0.4 LSB, an INL less than 0.5 LSB, and an ENOB of 9.9 bits. It can be integrated with micro-sensors to monolithically form highly sensitive, reliable and intelligent measurement devices.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC\",\"authors\":\"Lungui Zhong, Haigang Yang, Chong Zhang\",\"doi\":\"10.1109/ICASIC.2007.4415719\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a Charge Redistribution Successive Approximation Register ADC designed in a 0.35-mum standard CMOS process. The total power consumption is only 4.6 mW, and a resolution of 10 bits is achieved. The ADC maintains a maximum DNL of less than 0.4 LSB, an INL less than 0.5 LSB, and an ENOB of 9.9 bits. It can be integrated with micro-sensors to monolithically form highly sensitive, reliable and intelligent measurement devices.\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415719\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415719","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC
This paper presents a Charge Redistribution Successive Approximation Register ADC designed in a 0.35-mum standard CMOS process. The total power consumption is only 4.6 mW, and a resolution of 10 bits is achieved. The ADC maintains a maximum DNL of less than 0.4 LSB, an INL less than 0.5 LSB, and an ENOB of 9.9 bits. It can be integrated with micro-sensors to monolithically form highly sensitive, reliable and intelligent measurement devices.
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