基于16MHz SoC平台的高集成8mW H.264/AVC主配置文件实时CIF视频解码器

Huan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Y. Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, P. Chao, Wei-Cheng Hung, Kai-Yuan Jan
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引用次数: 6

摘要

提出了一种用于H.264/AVC主配置文件视频的硬连线解码器原型。本设计以压缩后的H.264/AVC码流作为输入,并产生可显示的视频帧作为输出。我们将解码器核心与AMBA-AHB总线接口封装,并将其集成到多媒体SoC平台中。在IP和系统级别上提出了一些架构创新,以在非常低的工作频率下实现非常高的性能。我们的FPGA演示系统运行在16MHz,能够以每秒30帧的速度实时解码CIF(352乘以288)视频。此外,我们考虑到系统成本,这样只需要一个外部SDRAM,内存流量最小化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform
We present a hardwired decoder prototype for H.264/AVC main profile video. Our design takes as its input compressed H.264/AVC bit-stream and produces as its output video frames ready for display. We wrap the decoder core with an AMBA-AHB bus interface and integrate it into a multimedia SoC platform. Several architectural innovations at both IP and system levels are proposed to achieve very high performance at very low operating frequency. Running at 16MHz, our FPGA demo system is able to real-time decode CIF (352 times 288) video at 30 frames per second. Moreover, we take system cost into consideration such that only a single external SDRAM is needed and memory traffic minimized.
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