FSS块匹配运动估计的并行处理结构

2011 International Conference on Communications, Computing and Control Applications (CCCA) Pub Date : 2011-03-03 DOI:10.1109/CCCA.2011.6031442

S. Dhahri, A. Zitouni, R. Tourki

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引用次数: 1

摘要

运动估计(ME)是提高压缩比的关键因素。然而，ME涉及高计算复杂度。主要目标是在不降低图像质量的情况下减少执行时间。本文提出了一种四步搜索块匹配运动估计的高并行处理架构。该方法提出了一种由9个处理单元并行处理的体系结构。利用VHDL和ASIC (CMOS 45nm)对该体系结构进行了仿真和合成。综合实验结果表明，所提出的体系结构具有较高的实时运动估计性能。

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A parallel processing architecture for FSS block-matching motion estimation

Motion Estimation (ME) is a key factor for achieving enhanced compression ratio. However, ME involves high computational complexity. The main goal is to reduce the execution time without reducing image quality. In this paper, a proposed high parallel processing architecture is presented for four-step search block-matching motion estimation. The proposed method develops an architecture which using 9 processing-elements (PE) and processes them in parallel. The architecture has been simulated and synthesized with VHDL and ASIC (CMOS 45nm). Synthesize results show that the proposed architecture achieves a high performance for real time motion estimation.

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2011 International Conference on Communications, Computing and Control Applications (CCCA)

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