{"title":"利用通道离子注入的自对准反良好掺杂技术及其在0.25 /spl μ m CMOS工艺中的应用","authors":"H. Nakamura, T. Horiuchi","doi":"10.1109/VLSIT.1995.520861","DOIUrl":null,"url":null,"abstract":"A new self-aligned counter doping technology intentionally utilizing the channeling effect of ion implantation is presented. A 50%-70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for a 0.25 /spl mu/m CMOS inverter chain under 0.9 V operation.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A self-aligned counter well-doping technology utilizing channeling ion implantation and its application to 0.25 /spl mu/m CMOS process\",\"authors\":\"H. Nakamura, T. Horiuchi\",\"doi\":\"10.1109/VLSIT.1995.520861\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new self-aligned counter doping technology intentionally utilizing the channeling effect of ion implantation is presented. A 50%-70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for a 0.25 /spl mu/m CMOS inverter chain under 0.9 V operation.\",\"PeriodicalId\":328379,\"journal\":{\"name\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1995.520861\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520861","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A self-aligned counter well-doping technology utilizing channeling ion implantation and its application to 0.25 /spl mu/m CMOS process
A new self-aligned counter doping technology intentionally utilizing the channeling effect of ion implantation is presented. A 50%-70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for a 0.25 /spl mu/m CMOS inverter chain under 0.9 V operation.
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