对重定时中合成应用正确性的建设性探讨

D. Eisenbiegler, Ramayya Kumar, C. Blumenröhr
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引用次数: 10

摘要

本文致力于正确的合成。通过正确的综合,我们的意思是,有一个数学证明告诉我们,输出电路的描述满足输入电路的描述。有几种方法可以实现正确的合成。在本文中,我们提出了一种新的方法,它集成了传统的综合算法,从而保证了相同的设计质量。我们的方法是完全自动化的,尽管它是基于定理证明器中的规则应用程序。我们将我们在重新计时领域的结果与其他方法进行比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A constructive approach towards correctness of synthesis-application within retiming
This paper is dedicated to correct synthesis. By correct synthesis we mean, that there is a mathematical proof telling us, that the output circuit description fulfils the input circuit description. There are several ways to achieve correct synthesis. In this paper, we present a novel approach which integrates conventional synthesis algorithms thus guaranteeing the same quality of designs. Our approach is fully automatic, although it is based on rule applications within a theorem prover. We compare our results in the area of retiming to other approaches.
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