一个14b 100MS/s数字自校准流水线ADC在0.13/spl μ m CMOS

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696123

P. Bogner, F. Kuttner, C. Kropf, T. Hartig, Markus Burian, Hermann Eul

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引用次数: 24

摘要

采用0.13 μ m数字CMOS工艺实现了14b多位/级流水线ADC。模拟电路的增益和匹配误差通过允许使用低增益运算放大器的数字校准方案进行补偿。通过引入电荷补偿方案，达到了低功耗的目的

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A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13/spl mu/m CMOS

A 14b multi-bit-per-stage pipelined ADC is implemented in a 0.13mum digital CMOS process. The gain and matching errors of the analog circuitry are compensated by a digital calibration scheme that allows the usage of a low-gain op-amp. A low power consumption has been reached by introducing a charge compensation scheme

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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