{"title":"采用22nm技术的6T, 5T和4T SRAM电池的比较","authors":"R. Rollini, Jenyfal Sampson, P. Sivakumar","doi":"10.1109/ICEICE.2017.8191924","DOIUrl":null,"url":null,"abstract":"The parameters such as Write Delay, Read Delay, Leakage Power, assumes an imperative part in the present day CMOS innovation. This paper examined about the near investigation of different SRAM cells, for example, 6T, 5T and 4T utilizing 22nm innovation. At the point when looking at 6T and 4T, the 4T SRAM cell has the efficient output. The leakage power is reduced considerably in 5T SRAM cell. This relative study is mimicked utilizing TANNER TOOL.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Comparison on 6T, 5T and 4T SRAM cell using 22nm technology\",\"authors\":\"R. Rollini, Jenyfal Sampson, P. Sivakumar\",\"doi\":\"10.1109/ICEICE.2017.8191924\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The parameters such as Write Delay, Read Delay, Leakage Power, assumes an imperative part in the present day CMOS innovation. This paper examined about the near investigation of different SRAM cells, for example, 6T, 5T and 4T utilizing 22nm innovation. At the point when looking at 6T and 4T, the 4T SRAM cell has the efficient output. The leakage power is reduced considerably in 5T SRAM cell. This relative study is mimicked utilizing TANNER TOOL.\",\"PeriodicalId\":110529,\"journal\":{\"name\":\"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEICE.2017.8191924\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEICE.2017.8191924","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Comparison on 6T, 5T and 4T SRAM cell using 22nm technology
The parameters such as Write Delay, Read Delay, Leakage Power, assumes an imperative part in the present day CMOS innovation. This paper examined about the near investigation of different SRAM cells, for example, 6T, 5T and 4T utilizing 22nm innovation. At the point when looking at 6T and 4T, the 4T SRAM cell has the efficient output. The leakage power is reduced considerably in 5T SRAM cell. This relative study is mimicked utilizing TANNER TOOL.
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