利用FinFET技术设计一种新型节能且过程免疫的Schmitt触发电路

Umayia Mushtaqa, Md. Waseem Akrama, Dinesh Prasada, Bal Chand Nagarb
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引用次数: 0

摘要

MOS(金属氧化物半导体)器件的持续缩放导致泄漏功耗急剧增加,从而总体上增加了总功耗。这是由于短信道效应的增加。FinFET器件具有减少短通道效应的能力,因此也降低了功耗。本文利用ASAP7 PDK(一种7nm FinFET预测工艺设计套件)在7nm工艺节点上提出了基于LCNT(漏控NMOS晶体管)技术的短栅FinFET Schmitt触发器,并与未采用LCNT技术的Schmitt触发器进行了对比分析。仿真结果表明,与未采用LCNT技术的Schmitt触发器相比,采用LCNT技术的Schmitt触发器的平均功耗和功率延迟积分别降低了36.97%和35.6%。采用蒙特卡罗方法对±10%工艺、电压和温度(PVT)变化在3 σ高斯分布下的可靠性分析表明,LCNT FinFET Schmitt触发器比7nm工艺节点的FinFET Schmitt触发器具有更好的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology
Continuous scaling of MOS (Metal oxide semiconductor) devices gives rise to drastic increase in leakage power dissipation, which overall increases the total power dissipation. This happens due to increase in short channel effects. FinFET device has the capability to reduce short channel effects, hence reduces power dissipation as well. In this paper short-gate FinFET (fin type field effect transistor) based Schmitt trigger using LCNT (Leakage Control NMOS transistor) technique is proposed using ASAP7 PDK (A 7nm FinFET Predictive process design kit) at 7nm technology node and comparative analysis is provided with the one without LCNT technique. The simulated results shows that FinFET based Schmitt trigger using LCNT technique reduces average power dissipation and power delay product (PDP) by 36.97% and 35.6%, respectively compared to one without FinFET LCNT technique. The reliability analysis using Monte Carlo approach at ±10% process, voltage and temperature (PVT) variation under 3 σ Gaussian distribution shows that LCNT FinFET Schmitt trigger provides better performance compared to FinFET Schmitt trigger at 7nm technology node.
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