A Study of Stored Charge Interference and Fringing Field Effects in Sub-30nm Charge-Trapping NAND Flash

The interference and fringing field effects beyond sub-30 nm node charge-trapping(CT) NAND Flash are studied critically using 3D simulation. Due to the relatively large EOT (>15 nm) compared to the device dimension (F), the most severe interference comes from adjacent pass-gate WL bias disturb through the edge fringing field effect. On the other hand, the program charges in adjacent devices generate only minor interference effect (<200 mV) down to 25 nm node. Low-K spacer between WL's is very effective in suppressing the pass-gate interference due to the suppressed fringing field effect. For the first time we propose that low-K spacer can improve the short-channel effect as well as program/erase characteristics. The physical reason is that low-K spacer can confine the electrical field inside the channel thus improve the device performances. By suitably engineering the low-K spacer, p-well/junction and EOT we suggest that scaling of CT NAND Flash beyond 15 nm is quite feasible.