{"title":"多模可重构模拟基带与I/Q校准用于GNSS接收机","authors":"Zheng Song, Nan Qi, B. Chi, Zhihua Wang","doi":"10.1109/ASPDAC.2014.6742858","DOIUrl":null,"url":null,"abstract":"A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers is presented. The baseband circuit consists of an I/Q calibration circuit, a reconfigurable complex band-pass filter (C-BPF) and an AGC loop. It provides I/Q mismatch auto-calibration with the aid of a FPGA. The 3rd/ 5th-order reconfigurable C-BPF supports various bandwidths from 2.2 to 10 MHz and with different center frequencies from 3.996 to 16 MHz. The AGC loop features 5-50 dB gain range and 1 dB step, and digital AGC algorithms. The auto DC-offset cancellation is also integrated on-chip. The analog baseband circuit has been implemented in 180 nm CMOS and consumes 6.5-13 mA variable current thanks to the power scaling technique. The measured image-rejection ratio is 45-55 dB, improved by 22 dB after I/Q calibration.","PeriodicalId":234635,"journal":{"name":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers\",\"authors\":\"Zheng Song, Nan Qi, B. Chi, Zhihua Wang\",\"doi\":\"10.1109/ASPDAC.2014.6742858\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers is presented. The baseband circuit consists of an I/Q calibration circuit, a reconfigurable complex band-pass filter (C-BPF) and an AGC loop. It provides I/Q mismatch auto-calibration with the aid of a FPGA. The 3rd/ 5th-order reconfigurable C-BPF supports various bandwidths from 2.2 to 10 MHz and with different center frequencies from 3.996 to 16 MHz. The AGC loop features 5-50 dB gain range and 1 dB step, and digital AGC algorithms. The auto DC-offset cancellation is also integrated on-chip. The analog baseband circuit has been implemented in 180 nm CMOS and consumes 6.5-13 mA variable current thanks to the power scaling technique. The measured image-rejection ratio is 45-55 dB, improved by 22 dB after I/Q calibration.\",\"PeriodicalId\":234635,\"journal\":{\"name\":\"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-02-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.2014.6742858\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.2014.6742858","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers
A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers is presented. The baseband circuit consists of an I/Q calibration circuit, a reconfigurable complex band-pass filter (C-BPF) and an AGC loop. It provides I/Q mismatch auto-calibration with the aid of a FPGA. The 3rd/ 5th-order reconfigurable C-BPF supports various bandwidths from 2.2 to 10 MHz and with different center frequencies from 3.996 to 16 MHz. The AGC loop features 5-50 dB gain range and 1 dB step, and digital AGC algorithms. The auto DC-offset cancellation is also integrated on-chip. The analog baseband circuit has been implemented in 180 nm CMOS and consumes 6.5-13 mA variable current thanks to the power scaling technique. The measured image-rejection ratio is 45-55 dB, improved by 22 dB after I/Q calibration.