基于NOR门的高速、低功耗16位0.25 /spl mu/m GaAs二进制前导进位(BLC)加法器，用于无线视频通信

1999 IEEE MTT-S International Topical Symposium on Technologies for Wireless Applications (Cat. No. 99TH8390) Pub Date : 1900-01-01 DOI:10.1109/MTTTWA.1999.755145

T. Enomoto, A. Hirobe, T. Satoh, M. Fujii, N. Yoshida, S. Wada, M. Tokushima

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引用次数: 1

摘要

采用0.25-/spl μ m GaAs HJFET技术制备了一种快速、低功耗、小型的16位加法器，用于未来的无线视频通信。该加法器采用基于NOR门的负逻辑二进制超前进位(BLC)结构，在0.6 V电源电压下工作在1.67 GHz的最大时钟频率下，功耗为134.4 mW。有效面积为1.6 mm/sup /，约有1,230个fet。

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A high-speed, low-power 16-bit 0.25 /spl mu/m GaAs binary look-ahead carry (BLC) adder based on NOR gates for wireless video communication

A fast, low-power, and small 16-bit adder was fabricated using 0.25-/spl mu/m GaAs HJFET technology for future wireless video communication. This adder, which uses negative logic binary look-ahead carry (BLC) structure based on NOR gates, operates at the maximum clock frequency of 1.67 GHz and consumes 134.4 mW at a supply voltage of 0.6 V. The active area is 1.6 mm/sup 2/ and there are about 1,230 FETs.

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1999 IEEE MTT-S International Topical Symposium on Technologies for Wireless Applications (Cat. No. 99TH8390)

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