Mădalina Elena Bundaru, D. Dobrescu, E. Franti, M. Enachescu, M. Dascalu, L. Dobrescu
{"title":"增强型纹波阻断器","authors":"Mădalina Elena Bundaru, D. Dobrescu, E. Franti, M. Enachescu, M. Dascalu, L. Dobrescu","doi":"10.1109/smicnd.2019.8923768","DOIUrl":null,"url":null,"abstract":"The present paper introduces a Ripple blocker architecture having a high power supply rejection ratio, as the main feature. The specific performance circuit parameters, the block circuit, the main sub-circuits of the designed Ripple blocker together with the transistor level circuits are presented. The Ripple blocker is provided with a current sense circuit that ensures the capability to maintain the desired behavior with a wide range of load resistor values.","PeriodicalId":151985,"journal":{"name":"2019 International Semiconductor Conference (CAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Enhanced Ripple Blocker\",\"authors\":\"Mădalina Elena Bundaru, D. Dobrescu, E. Franti, M. Enachescu, M. Dascalu, L. Dobrescu\",\"doi\":\"10.1109/smicnd.2019.8923768\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The present paper introduces a Ripple blocker architecture having a high power supply rejection ratio, as the main feature. The specific performance circuit parameters, the block circuit, the main sub-circuits of the designed Ripple blocker together with the transistor level circuits are presented. The Ripple blocker is provided with a current sense circuit that ensures the capability to maintain the desired behavior with a wide range of load resistor values.\",\"PeriodicalId\":151985,\"journal\":{\"name\":\"2019 International Semiconductor Conference (CAS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Semiconductor Conference (CAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/smicnd.2019.8923768\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Semiconductor Conference (CAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/smicnd.2019.8923768","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The present paper introduces a Ripple blocker architecture having a high power supply rejection ratio, as the main feature. The specific performance circuit parameters, the block circuit, the main sub-circuits of the designed Ripple blocker together with the transistor level circuits are presented. The Ripple blocker is provided with a current sense circuit that ensures the capability to maintain the desired behavior with a wide range of load resistor values.
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