{"title":"基于CMOS技术实现的LMS FIR并行自适应滤波器","authors":"R. Dlugosz, T. Talaśka, T. Nikolic, G. Nikolic","doi":"10.1109/MIEL.2019.8889595","DOIUrl":null,"url":null,"abstract":"The paper presents an adaptive Finite Impulse Response (FIR) filter implemented at the transistor level in the CMOS technology. The filter is based on the LMS (least mean squares) adaptation algorithm. We applied several solutions that allows for simplifications of the hardware structure of the filter. One of them is to eliminate the division operation, replacing it with the bit-shifting operation. Parallel operation of the blocks representing particular filter coefficients allows to achieve operating speeds that are independent on the filter order. Main components of the filter were designed in the CMOS 130 nm technology and verified by means of laboratory tests, while selected structures of the overall filter have been examined by means of transistor-level simulations.","PeriodicalId":391606,"journal":{"name":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Parallel Adaptive LMS FIR Filter Realized in CMOS Technology\",\"authors\":\"R. Dlugosz, T. Talaśka, T. Nikolic, G. Nikolic\",\"doi\":\"10.1109/MIEL.2019.8889595\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents an adaptive Finite Impulse Response (FIR) filter implemented at the transistor level in the CMOS technology. The filter is based on the LMS (least mean squares) adaptation algorithm. We applied several solutions that allows for simplifications of the hardware structure of the filter. One of them is to eliminate the division operation, replacing it with the bit-shifting operation. Parallel operation of the blocks representing particular filter coefficients allows to achieve operating speeds that are independent on the filter order. Main components of the filter were designed in the CMOS 130 nm technology and verified by means of laboratory tests, while selected structures of the overall filter have been examined by means of transistor-level simulations.\",\"PeriodicalId\":391606,\"journal\":{\"name\":\"2019 IEEE 31st International Conference on Microelectronics (MIEL)\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 31st International Conference on Microelectronics (MIEL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIEL.2019.8889595\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 31st International Conference on Microelectronics (MIEL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIEL.2019.8889595","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Parallel Adaptive LMS FIR Filter Realized in CMOS Technology
The paper presents an adaptive Finite Impulse Response (FIR) filter implemented at the transistor level in the CMOS technology. The filter is based on the LMS (least mean squares) adaptation algorithm. We applied several solutions that allows for simplifications of the hardware structure of the filter. One of them is to eliminate the division operation, replacing it with the bit-shifting operation. Parallel operation of the blocks representing particular filter coefficients allows to achieve operating speeds that are independent on the filter order. Main components of the filter were designed in the CMOS 130 nm technology and verified by means of laboratory tests, while selected structures of the overall filter have been examined by means of transistor-level simulations.