高性能CMOS栅极介电尺度:从SiO2到高k

Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765) Pub Date : 2003-12-19 DOI:10.1109/IWGI.2003.159198

R. Chau, S. Datta, M. Doczy, J. Kavalieros, M. Metz

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引用次数: 64

摘要

我们已经成功地展示了非常高性能的PMOS和NMOS晶体管，这些晶体管具有高k /金属栅极栅极堆栈，具有适合体硅p和n通道的阈值电压。我们相信高k /金属栅极是45纳米高性能逻辑技术节点的一种选择。

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Gate dielectric scaling for high-performance CMOS: from SiO2 to high-K

We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45 nm high-performance logic technology node.

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Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765)

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