一种新的超低功耗射频集成电路功率优化技术

ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design Pub Date : 2006-10-04 DOI:10.1145/1165573.1165639

A. Shameli, P. Heydari

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引用次数: 48

摘要

提出了一种新的超低功耗射频集成电路的功率优化技术。为MOS晶体管定义了一个新的性能指标，即gmfT/ID，它同时考虑了单位增益频率和电流消耗。分析和实验均表明，gmfT/ID在中等逆温区达到最大值。然后，利用所提出的方法，设计并制作了一个功率优化的有源负载共门低噪声放大器(LNA)，工作频率为950MHz，采用CMOS 0.18mum工艺。测量结果表明，噪声系数(NF)为4.9dB，信号增益为15.6dB，功耗仅为100muW

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A Novel Power Optimization Technique for Ultra-Low Power RFICs

This paper presents a novel power optimization technique for ultra-low power (ULP) RFICs. A new figure of merit, namely the g_mf_T- to-current ratio (g_mf_T/I_D), is defined for a MOS transistor, which accounts for both the unity-gain frequency and current consumption. It is demonstrated both analytically and experimentally that the g_mf_T/I_D reaches its maximum value in moderate inversion region. Next, using the proposed method, a power optimized common-gate low-noise amplifier (LNA) with active load has been designed and fabricated in a CMOS 0.18mum process operating at 950MHz. Measurement results show a noise-figure (NF) of 4.9dB and a small signal gain of 15.6dB with a record-breaking power dissipation of only 100muW

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ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design

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