A partitioning and storage based built-in test pattern generation method for delay faults in scan circuits

We describe a built-in test pattern generation method for delay faults in scan circuits based on partitioning and storage of test sets. Under this method, a precomputed test set is partitioned into several sets containing values of primary inputs or state variables. The on-chip test set is obtained by implementing the Cartesian product of the stored sets. The sizes of the sets are minimized before they are stored on-chip in order to reduce the storage requirements and the test application time. The delay fault model we consider is the transition fault model.