0.89 mW on-chip jitter-measurement circuit for high speed clock with sub-picosecond resolution

This paper demonstrates an all digital fully on-chip jitter measurement circuit with sub-picosecond resolution that can be used with or without an external reference. The circuit is integrated on a CMOS chip and outputs a digital code proportional to the jitter of high speed clock signals. It achieves low error while consuming less than 0.89 mW by using a low-speed stochastic under-sampler to approximate high speed sampling. Test chips were fabricated in a 65 nm CMOS process with an active area of 0.015 mm2. The absolute jitter and period jitter of a 6 GHz test clock were measured with root mean square error of 0.102 ps and 0.308 ps, respectively.