G. Minghui, Zhao Haijun, A. Bandyopadhyay, C. Jiang, Foo Pang Dow
{"title":"高速低成本的射频应用BiCMOS采用轮廓工程","authors":"G. Minghui, Zhao Haijun, A. Bandyopadhyay, C. Jiang, Foo Pang Dow","doi":"10.1109/ICSICT.1998.785845","DOIUrl":null,"url":null,"abstract":"This paper describes a low cost, CMOS foundry compatible BiCMOS process for 1.9 GHz RF applications. It keeps the simple feature of the triple-well single-poly approach while achieving much higher f/sub T/ by utilizing novel c-well profile engineering to reduce base and collector series resistance.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High speed low cost BiCMOS for RF applications using profile engineering\",\"authors\":\"G. Minghui, Zhao Haijun, A. Bandyopadhyay, C. Jiang, Foo Pang Dow\",\"doi\":\"10.1109/ICSICT.1998.785845\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a low cost, CMOS foundry compatible BiCMOS process for 1.9 GHz RF applications. It keeps the simple feature of the triple-well single-poly approach while achieving much higher f/sub T/ by utilizing novel c-well profile engineering to reduce base and collector series resistance.\",\"PeriodicalId\":286980,\"journal\":{\"name\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"volume\":\"113 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1998.785845\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1998.785845","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High speed low cost BiCMOS for RF applications using profile engineering
This paper describes a low cost, CMOS foundry compatible BiCMOS process for 1.9 GHz RF applications. It keeps the simple feature of the triple-well single-poly approach while achieving much higher f/sub T/ by utilizing novel c-well profile engineering to reduce base and collector series resistance.