大型冗余RAMs成品率建模与优化

1990 Proceedings. International Conference on Wafer Scale Integration Pub Date : 1990-01-23 DOI:10.1109/ICWSI.1990.63911

K. Ganapathy, A.D. Singh, D. Pradhan

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引用次数: 2

摘要

提出并分析了冗余的大面积TRAM结构(64 ~ 512 Mbit)在冗余水平上的变化，确定了提高成品率的最佳冗余组织。采用分层冗余方案实现缺陷容限，并采用复合泊松模型对冗余RAM的良率进行建模。结果显示了局部冗余方案与全局冗余方案之间的权衡。

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Yield modeling and optimization of large redundant RAMs

Presents and analyzes redundant large area TRAM architectures (64 to 512 Mbit) for variations in redundancy level and determine the optimal redundancy organization for yield enhancement. A hierarchical redundancy scheme is used for defect tolerance and the yield of the redundant RAM is modelled using a compounded Poisson model. Results are presented that show the tradeoff in local versus global redundancy schemes for TRAM.<>

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1990 Proceedings. International Conference on Wafer Scale Integration

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