{"title":"紧凑N+Poly/Nwell变容管的高频特性研究","authors":"Y. Morandini, J. Larchanche, C. Gaquière","doi":"10.1109/SMIC.2008.48","DOIUrl":null,"url":null,"abstract":"The high frequency characterization of a new waffle layout for N+Poly/Nwell varactor has been studied in STMicroelectronics 65 nm CMOS process. We compare this new waffle layout with model of standard multifingers varactor. In addition to the area saving, the waffle MOS varactor also provides enhancement to the RF merit figure of varactor through the serial resistance and substrate capacitance improvement.","PeriodicalId":350325,"journal":{"name":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"High Frequency Characterization of Compact N+Poly/Nwell Varactor Using Waffle-Layout\",\"authors\":\"Y. Morandini, J. Larchanche, C. Gaquière\",\"doi\":\"10.1109/SMIC.2008.48\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The high frequency characterization of a new waffle layout for N+Poly/Nwell varactor has been studied in STMicroelectronics 65 nm CMOS process. We compare this new waffle layout with model of standard multifingers varactor. In addition to the area saving, the waffle MOS varactor also provides enhancement to the RF merit figure of varactor through the serial resistance and substrate capacitance improvement.\",\"PeriodicalId\":350325,\"journal\":{\"name\":\"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-02-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMIC.2008.48\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMIC.2008.48","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Frequency Characterization of Compact N+Poly/Nwell Varactor Using Waffle-Layout
The high frequency characterization of a new waffle layout for N+Poly/Nwell varactor has been studied in STMicroelectronics 65 nm CMOS process. We compare this new waffle layout with model of standard multifingers varactor. In addition to the area saving, the waffle MOS varactor also provides enhancement to the RF merit figure of varactor through the serial resistance and substrate capacitance improvement.