高压NMOS采用0.5 /spl μ m CMOS技术,用于快速开关应用

P. Santos, H. Quaresma, A.P. Silva, M. Lança
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引用次数: 0

摘要

本文描述了在深亚微米0.5 /spl μ m CMOS工艺中实现高压NMOS器件,仅依靠设计布局策略。实验表明,在其他电气参数保持在合理值的情况下,使用Gate-Shift技术将器件击穿电压提高到29 V左右是可行的。从这些高压NMOS晶体管的可用性可以得出结论,设计人员可以采用上一代CMOS工艺来开发成本智能的功率集成电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High-voltage NMOS in 0.5 /spl mu/m CMOS technology for fast switching applications
This paper describes high-voltage NMOS devices implementation in a deep submicron 0.5 /spl mu/m CMOS process, only resorting to design layout strategies. Experiments show the viability of using the Gate-Shift technique to improve devices breakdown voltage to circa 29 V, while other electrical parameters are kept at reasonable values. From the availability of these high voltage NMOS transistors it can be concluded that designers can resort to last generation CMOS processes to develop cost smart power integrated circuits.
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