Z. Chen, N. Araki, Y. Kim, T. Fukuda, K. Sakui, T. Nakamura, T. Kobayashi, T. Obara, T. Ohba
{"title":"背面缺陷对3-5 μm Si晶圆超薄dram器件特性的影响","authors":"Z. Chen, N. Araki, Y. Kim, T. Fukuda, K. Sakui, T. Nakamura, T. Kobayashi, T. Obara, T. Ohba","doi":"10.23919/ICEP55381.2022.9795532","DOIUrl":null,"url":null,"abstract":"To clarify the impact of backside defects on the device characteristics during wafer ultra-thinning, 20 nm-node DRAM Si wafers were thinned down to a thickness of 3-5 μm and evaluated. The dependences of the DRAM characteristics on the depth of backside defects, Si thickness, and chip position within a 300-mm wafer are described.","PeriodicalId":413776,"journal":{"name":"2022 International Conference on Electronics Packaging (ICEP)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Impact of Backside Defects on Device Characteristics of Ultra-Thin DRAMs with 3-5 μm Si Wafers for Bumpless Build Cube (BBCube) Application\",\"authors\":\"Z. Chen, N. Araki, Y. Kim, T. Fukuda, K. Sakui, T. Nakamura, T. Kobayashi, T. Obara, T. Ohba\",\"doi\":\"10.23919/ICEP55381.2022.9795532\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To clarify the impact of backside defects on the device characteristics during wafer ultra-thinning, 20 nm-node DRAM Si wafers were thinned down to a thickness of 3-5 μm and evaluated. The dependences of the DRAM characteristics on the depth of backside defects, Si thickness, and chip position within a 300-mm wafer are described.\",\"PeriodicalId\":413776,\"journal\":{\"name\":\"2022 International Conference on Electronics Packaging (ICEP)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-05-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 International Conference on Electronics Packaging (ICEP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/ICEP55381.2022.9795532\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Electronics Packaging (ICEP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/ICEP55381.2022.9795532","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of Backside Defects on Device Characteristics of Ultra-Thin DRAMs with 3-5 μm Si Wafers for Bumpless Build Cube (BBCube) Application
To clarify the impact of backside defects on the device characteristics during wafer ultra-thinning, 20 nm-node DRAM Si wafers were thinned down to a thickness of 3-5 μm and evaluated. The dependences of the DRAM characteristics on the depth of backside defects, Si thickness, and chip position within a 300-mm wafer are described.
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