{"title":"用流程图验证寄存器传输级的合成电路","authors":"F. Feldbusch, Ramayya Kumar","doi":"10.1109/EDAC.1991.206351","DOIUrl":null,"url":null,"abstract":"Presents a new approach to the verification of automatically synthesized register transfer structures. Horizontal verification is performed on the flow graph which is largely a syntax independent representation of behavior. After extracting a flow graph from the register transfer structure by symbolic simulation, the extracted and the specified flow graphs are normalized into a normal form. A comparison of the normalized flow graphs gives the proof of correctness. The various synthesis steps have been classified into five classes and the normalization procedures have been evaluated.<<ETX>>","PeriodicalId":425087,"journal":{"name":"Proceedings of the European Conference on Design Automation.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Verification of synthesized circuits at register transfer level with flow graphs\",\"authors\":\"F. Feldbusch, Ramayya Kumar\",\"doi\":\"10.1109/EDAC.1991.206351\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a new approach to the verification of automatically synthesized register transfer structures. Horizontal verification is performed on the flow graph which is largely a syntax independent representation of behavior. After extracting a flow graph from the register transfer structure by symbolic simulation, the extracted and the specified flow graphs are normalized into a normal form. A comparison of the normalized flow graphs gives the proof of correctness. The various synthesis steps have been classified into five classes and the normalization procedures have been evaluated.<<ETX>>\",\"PeriodicalId\":425087,\"journal\":{\"name\":\"Proceedings of the European Conference on Design Automation.\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-02-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the European Conference on Design Automation.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAC.1991.206351\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the European Conference on Design Automation.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAC.1991.206351","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Verification of synthesized circuits at register transfer level with flow graphs
Presents a new approach to the verification of automatically synthesized register transfer structures. Horizontal verification is performed on the flow graph which is largely a syntax independent representation of behavior. After extracting a flow graph from the register transfer structure by symbolic simulation, the extracted and the specified flow graphs are normalized into a normal form. A comparison of the normalized flow graphs gives the proof of correctness. The various synthesis steps have been classified into five classes and the normalization procedures have been evaluated.<>
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