边界扫描实现的单元设计

2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI:10.1109/ICMEL.2000.838791

V. Panic, S. Jankovic, D. Milovanovic, V. Litovski

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引用次数: 0

摘要

本文提出了一种边界扫描单元设计的新方法。在回顾了pcb测试中的主要问题后，对边界扫描标准进行了简要概述。此外，还对边界扫描单元进行了逻辑级合成。这些单元的逻辑级设计用于布局生成。从生成的布局中提取各电路的网表，然后用Alecsis2.4进行仿真。仿真结果与期望值进行了比较，并以适当的方式给出了结果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Cell design for boundary-scan implementation

This paper gives a new approach in cell design for boundary-scan implementation. After recalling on major problems in PCBs testing, a short overview of boundary-scan standard is given. Furthermore, logic level synthesis of boundary-scan cells are done. Logic level design of these cells are used for layout generation. From generated layout, netlist for each circuit is extracted, and after that simulated by Alecsis2.4. The simulation results are compared with expected values, and are presented in appropriate manner.

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来源期刊

2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)

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