{"title":"BO-MOS RAM单元","authors":"J. Sakurai","doi":"10.1109/IEDM.1978.189386","DOIUrl":null,"url":null,"abstract":"A new structure and its fabrication process of MOS dynamic RAM cells are presented for higher density and potentially higher yield. The buried oxide MOS RAM (BO-MOS RAM) cell consists of a planar MOS transfer gate and a buried storage capacitor of N+diffusion. Its operation is identical to that of the conventional one-transistor dynamic RAM cell. The resulting advantages are (a) A cell size of 6F2with the minimum lithographic feature size F is achieved, which is equivalent to one-fifth to one-eighth of the conventional 16 Kbit or 64 Kbit RAM cell. (b) A combination of the smaller cell size and an elimination of the MOS capacitor should result in higher production yield as well as higher packing density in one-transistor dynamic RAM.","PeriodicalId":164556,"journal":{"name":"1978 International Electron Devices Meeting","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"The BO-MOS RAM cell\",\"authors\":\"J. Sakurai\",\"doi\":\"10.1109/IEDM.1978.189386\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new structure and its fabrication process of MOS dynamic RAM cells are presented for higher density and potentially higher yield. The buried oxide MOS RAM (BO-MOS RAM) cell consists of a planar MOS transfer gate and a buried storage capacitor of N+diffusion. Its operation is identical to that of the conventional one-transistor dynamic RAM cell. The resulting advantages are (a) A cell size of 6F2with the minimum lithographic feature size F is achieved, which is equivalent to one-fifth to one-eighth of the conventional 16 Kbit or 64 Kbit RAM cell. (b) A combination of the smaller cell size and an elimination of the MOS capacitor should result in higher production yield as well as higher packing density in one-transistor dynamic RAM.\",\"PeriodicalId\":164556,\"journal\":{\"name\":\"1978 International Electron Devices Meeting\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1978 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1978.189386\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1978 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1978.189386","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new structure and its fabrication process of MOS dynamic RAM cells are presented for higher density and potentially higher yield. The buried oxide MOS RAM (BO-MOS RAM) cell consists of a planar MOS transfer gate and a buried storage capacitor of N+diffusion. Its operation is identical to that of the conventional one-transistor dynamic RAM cell. The resulting advantages are (a) A cell size of 6F2with the minimum lithographic feature size F is achieved, which is equivalent to one-fifth to one-eighth of the conventional 16 Kbit or 64 Kbit RAM cell. (b) A combination of the smaller cell size and an elimination of the MOS capacitor should result in higher production yield as well as higher packing density in one-transistor dynamic RAM.
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