Bai Song Samuel Lee, Hang-Ji Liu, Xiaopeng Yu, Jer-Ming Chen, K. Yeo
{"title":"采用40nm CMOS的无电感5 ghz差分双稳压跨级联码跨阻放大器","authors":"Bai Song Samuel Lee, Hang-Ji Liu, Xiaopeng Yu, Jer-Ming Chen, K. Yeo","doi":"10.1109/ASICON47005.2019.8983663","DOIUrl":null,"url":null,"abstract":"This paper presents a new inductorless 5-GHz differential dual regulated cross-cascode transimpedance amplifier (DDRCCTIA) using UMC 40 nm CMOS technology. It consists of a differential cross-coupled input stage (DDRCC) that has a unique dual PMOS and NMOS regulated cascode loops as well as a frequency doubler with active inductor (FDAI) buffer stage. The design has a transimpedance gain of 62.5 dBΩ and bandwidth of 5.02 GHz. The power consumption is 7.34 mW from a 1.8 V supply, input referred noise current of 4.5 pA√Hz and a very small core area of 0.0018 mm2.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An Inductorless 5-GHz Differential Dual Regulated Cross-Cascode Transimpedance Amplifier using 40 nm CMOS\",\"authors\":\"Bai Song Samuel Lee, Hang-Ji Liu, Xiaopeng Yu, Jer-Ming Chen, K. Yeo\",\"doi\":\"10.1109/ASICON47005.2019.8983663\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new inductorless 5-GHz differential dual regulated cross-cascode transimpedance amplifier (DDRCCTIA) using UMC 40 nm CMOS technology. It consists of a differential cross-coupled input stage (DDRCC) that has a unique dual PMOS and NMOS regulated cascode loops as well as a frequency doubler with active inductor (FDAI) buffer stage. The design has a transimpedance gain of 62.5 dBΩ and bandwidth of 5.02 GHz. The power consumption is 7.34 mW from a 1.8 V supply, input referred noise current of 4.5 pA√Hz and a very small core area of 0.0018 mm2.\",\"PeriodicalId\":319342,\"journal\":{\"name\":\"2019 IEEE 13th International Conference on ASIC (ASICON)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 13th International Conference on ASIC (ASICON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON47005.2019.8983663\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 13th International Conference on ASIC (ASICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON47005.2019.8983663","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Inductorless 5-GHz Differential Dual Regulated Cross-Cascode Transimpedance Amplifier using 40 nm CMOS
This paper presents a new inductorless 5-GHz differential dual regulated cross-cascode transimpedance amplifier (DDRCCTIA) using UMC 40 nm CMOS technology. It consists of a differential cross-coupled input stage (DDRCC) that has a unique dual PMOS and NMOS regulated cascode loops as well as a frequency doubler with active inductor (FDAI) buffer stage. The design has a transimpedance gain of 62.5 dBΩ and bandwidth of 5.02 GHz. The power consumption is 7.34 mW from a 1.8 V supply, input referred noise current of 4.5 pA√Hz and a very small core area of 0.0018 mm2.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
