{"title":"POM:用于图像处理的处理器模型","authors":"Jean-Paul Theis, L. Thiele","doi":"10.1109/ICCD.1995.528829","DOIUrl":null,"url":null,"abstract":"In this paper, we describe a new processor model called Periodic Operation Model (POM) that is suitable for real time image processing. First we analyze existing image processing systems in order to situate our approach. Starting from the processor architecture, we derive the corresponding algorithm class by means of a novel hardware description. Then we address the allocation and scheduling problem. We show that allocation and scheduling can be decoupled in the mapping process related to POM-processor arrays and outline the principles of an optimal mapping trajectory. We describe the outline of a novel ILP-model for allocation of POM-processor arrays which takes into account array-topology and bus bandwidth constraints. Finally we discuss implementational aspects of the POM as well as applications in image processing. We especially show that POM-processor arrays can be integrated onto single chips, thereby allowing to achieve several GOPS processing power per chip.","PeriodicalId":281907,"journal":{"name":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"POM: a processor model for image processing\",\"authors\":\"Jean-Paul Theis, L. Thiele\",\"doi\":\"10.1109/ICCD.1995.528829\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we describe a new processor model called Periodic Operation Model (POM) that is suitable for real time image processing. First we analyze existing image processing systems in order to situate our approach. Starting from the processor architecture, we derive the corresponding algorithm class by means of a novel hardware description. Then we address the allocation and scheduling problem. We show that allocation and scheduling can be decoupled in the mapping process related to POM-processor arrays and outline the principles of an optimal mapping trajectory. We describe the outline of a novel ILP-model for allocation of POM-processor arrays which takes into account array-topology and bus bandwidth constraints. Finally we discuss implementational aspects of the POM as well as applications in image processing. We especially show that POM-processor arrays can be integrated onto single chips, thereby allowing to achieve several GOPS processing power per chip.\",\"PeriodicalId\":281907,\"journal\":{\"name\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.1995.528829\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.1995.528829","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we describe a new processor model called Periodic Operation Model (POM) that is suitable for real time image processing. First we analyze existing image processing systems in order to situate our approach. Starting from the processor architecture, we derive the corresponding algorithm class by means of a novel hardware description. Then we address the allocation and scheduling problem. We show that allocation and scheduling can be decoupled in the mapping process related to POM-processor arrays and outline the principles of an optimal mapping trajectory. We describe the outline of a novel ILP-model for allocation of POM-processor arrays which takes into account array-topology and bus bandwidth constraints. Finally we discuss implementational aspects of the POM as well as applications in image processing. We especially show that POM-processor arrays can be integrated onto single chips, thereby allowing to achieve several GOPS processing power per chip.