PCB参考时钟的紧凑型延迟匹配方案

2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI) Pub Date : 2017-08-01 DOI:10.1109/ISEMC.2017.8077897

Hanqiao Zhang, G. Ouyang, Kai Xiao, Beomtaek Lee

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引用次数: 0

摘要

提出了一种紧凑的PCB参考时钟延迟匹配方案。与传统的长度匹配方法相比，该方法可节省高达70%的面积。它还提供了设计和布局的灵活性。模拟了匹配网络的有效性、静电性能和组件变化的影响，并与传统方法进行了比较。

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Compact delay matching solution for reference clock in PCB

This paper proposes a compact delay matching solution for reference clock in PCB. The proposed method provides up to 70% area saving compared to the traditional length matching methods. It also provides design and layout flexibility. Effectiveness of the matching network, electrical static performance, and component variation impacts are simulated and compared to conventional methods.

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来源期刊

2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI)

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