基于标准0.18µm BCD平台的隔离型JFET设计及性能实验分析

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI:10.1109/ISPSD57135.2023.10147671

Dingxiang Ma, Yue Gao, Dican Hou, Zhangyi’an Yuan, M. Qiao, Shaowei Zhen, Bo Zhang

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引用次数: 0

摘要

本文基于标准的0.18µm BCD平台，通过实验研究了满足60V导通应用的两种JFET的设计。同时实现了-IV到- 6V的引脚电压范围，断态击穿电压(BVoFF)达到107V，甚至延伸到117V。利用p型埋层(PBL)，在不牺牲BVoFF和VP的情况下，可实现1.45mA的最大输出电流。此外，还分析了不同外加电压下的漏极抑制效应。考虑成品率，在不同的模具上测量了两种结构的BV OFF和vp，以说明其布局设计的稳定性。

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Isolated JFET Design and Performance Analyze by Experiment Based on Standard 0.18µm BCD Platform

This study investigates design of two kinds of JFET by experiment based on a standard 0.18µm BCD platform, satisfying the 60V on-state application. Meanwhile a range of pinch-off voltage (VP) from -IV to −6V is achieved and off-state breakdown voltage (BVoFF) reaches 107V even extending to 117V. By utilizing the P-type buried layer (PBL), maximum output current fabricated realizes 1.45mA without sacrificing BVoFF and VP. What's more, drain induced barrier lowering (DIBL) effect is analyzed with different applied voltages. Considering yield, BV OFF and V p of both structures are measured from different dies to illustrate its stability of layout design.

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2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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