M. D’Arco, L. Angrisani, P. Monsurrò, A. Trifiletti
{"title":"利用并行时间交错DAC核的高速AWG","authors":"M. D’Arco, L. Angrisani, P. Monsurrò, A. Trifiletti","doi":"10.1109/I2MTC43012.2020.9129138","DOIUrl":null,"url":null,"abstract":"An arbitrary waveform generator architecture that exploits multiple DAC cores to increase the sample rate with respect to AWG architectures based on an individual DAC is proposed. The processing operations necessary to distribute the waveform samples between the DAC cores are illustrated. The preliminary results highlighting the performance expected from the proposed architecture are shown.","PeriodicalId":227967,"journal":{"name":"2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High-speed AWG exploiting parallel time interleaved DAC cores\",\"authors\":\"M. D’Arco, L. Angrisani, P. Monsurrò, A. Trifiletti\",\"doi\":\"10.1109/I2MTC43012.2020.9129138\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An arbitrary waveform generator architecture that exploits multiple DAC cores to increase the sample rate with respect to AWG architectures based on an individual DAC is proposed. The processing operations necessary to distribute the waveform samples between the DAC cores are illustrated. The preliminary results highlighting the performance expected from the proposed architecture are shown.\",\"PeriodicalId\":227967,\"journal\":{\"name\":\"2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/I2MTC43012.2020.9129138\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/I2MTC43012.2020.9129138","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-speed AWG exploiting parallel time interleaved DAC cores
An arbitrary waveform generator architecture that exploits multiple DAC cores to increase the sample rate with respect to AWG architectures based on an individual DAC is proposed. The processing operations necessary to distribute the waveform samples between the DAC cores are illustrated. The preliminary results highlighting the performance expected from the proposed architecture are shown.