{"title":"嵌入式ram中数据和地址总线串扰故障的测试","authors":"Jiunn-Der Yu, Jin-Fu Li, Tsu-Wei Tseng","doi":"10.1109/VDAT.2007.373218","DOIUrl":null,"url":null,"abstract":"Random access memories (RAMs) have many long parallel wires which incur a greater probability for excessive crosstalk coupling effect. This paper presents a test algorithm for detecting crosstalk faults of address and data buses in RAMs. The test algorithm requires 12n+2m+2 Read/Write operations to cover 100% crosstalk faults for a RAM with m-bit addresses, n-bit data inputs/outputs. A BIST supporting March-CW and the proposed test is also implemented. Experimental results show that the area cost of the BIST is only about 3.1% for an 8 Ktimes16-bit RAM based on TSMC 0.18 mum standard cell library.","PeriodicalId":137915,"journal":{"name":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Testing Crosstalk Faults of Data and Address Buses in Embedded RAMs\",\"authors\":\"Jiunn-Der Yu, Jin-Fu Li, Tsu-Wei Tseng\",\"doi\":\"10.1109/VDAT.2007.373218\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Random access memories (RAMs) have many long parallel wires which incur a greater probability for excessive crosstalk coupling effect. This paper presents a test algorithm for detecting crosstalk faults of address and data buses in RAMs. The test algorithm requires 12n+2m+2 Read/Write operations to cover 100% crosstalk faults for a RAM with m-bit addresses, n-bit data inputs/outputs. A BIST supporting March-CW and the proposed test is also implemented. Experimental results show that the area cost of the BIST is only about 3.1% for an 8 Ktimes16-bit RAM based on TSMC 0.18 mum standard cell library.\",\"PeriodicalId\":137915,\"journal\":{\"name\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2007.373218\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2007.373218","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Testing Crosstalk Faults of Data and Address Buses in Embedded RAMs
Random access memories (RAMs) have many long parallel wires which incur a greater probability for excessive crosstalk coupling effect. This paper presents a test algorithm for detecting crosstalk faults of address and data buses in RAMs. The test algorithm requires 12n+2m+2 Read/Write operations to cover 100% crosstalk faults for a RAM with m-bit addresses, n-bit data inputs/outputs. A BIST supporting March-CW and the proposed test is also implemented. Experimental results show that the area cost of the BIST is only about 3.1% for an 8 Ktimes16-bit RAM based on TSMC 0.18 mum standard cell library.
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