{"title":"基于最大网络序列提取的预分配RDL路由","authors":"Jin-Tai Yan, Zhi-Wei Chen","doi":"10.1109/ICCD.2011.6081377","DOIUrl":null,"url":null,"abstract":"Given a set of IO connections between IO buffers and bump balls in a re-distribution routing layer, an efficient router is proposed to route all the IO connections for pre-assignment RDL routing in an area-IO flip-chip design. Based on the simplification of net renumbering and the extraction of the maximal net sequence for all the IO connections, all the connections can be firstly divided into local and global connections. After routing the global wires of all the local connections, the global wires of all the global connections are further assigned under the capacity constraint for RDL global routing. Finally, the global wires of all the IO connections are routed for RDL detailed routing by assigning feasible crossing points and physical paths. The experimental results show that our proposed pre-assignment RDL router can maintain 100% routability in 7 tested industrial circuits. Compared with Yan's pre-assignment RDL router[4] in total wirelength and CPU time, our proposed approach saves 3.7% of total wirelength and 27.0% of CPU time on the average.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Pre-assignment RDL routing via extraction of maximal net sequence\",\"authors\":\"Jin-Tai Yan, Zhi-Wei Chen\",\"doi\":\"10.1109/ICCD.2011.6081377\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Given a set of IO connections between IO buffers and bump balls in a re-distribution routing layer, an efficient router is proposed to route all the IO connections for pre-assignment RDL routing in an area-IO flip-chip design. Based on the simplification of net renumbering and the extraction of the maximal net sequence for all the IO connections, all the connections can be firstly divided into local and global connections. After routing the global wires of all the local connections, the global wires of all the global connections are further assigned under the capacity constraint for RDL global routing. Finally, the global wires of all the IO connections are routed for RDL detailed routing by assigning feasible crossing points and physical paths. The experimental results show that our proposed pre-assignment RDL router can maintain 100% routability in 7 tested industrial circuits. Compared with Yan's pre-assignment RDL router[4] in total wirelength and CPU time, our proposed approach saves 3.7% of total wirelength and 27.0% of CPU time on the average.\",\"PeriodicalId\":354015,\"journal\":{\"name\":\"2011 IEEE 29th International Conference on Computer Design (ICCD)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE 29th International Conference on Computer Design (ICCD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.2011.6081377\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE 29th International Conference on Computer Design (ICCD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2011.6081377","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Pre-assignment RDL routing via extraction of maximal net sequence
Given a set of IO connections between IO buffers and bump balls in a re-distribution routing layer, an efficient router is proposed to route all the IO connections for pre-assignment RDL routing in an area-IO flip-chip design. Based on the simplification of net renumbering and the extraction of the maximal net sequence for all the IO connections, all the connections can be firstly divided into local and global connections. After routing the global wires of all the local connections, the global wires of all the global connections are further assigned under the capacity constraint for RDL global routing. Finally, the global wires of all the IO connections are routed for RDL detailed routing by assigning feasible crossing points and physical paths. The experimental results show that our proposed pre-assignment RDL router can maintain 100% routability in 7 tested industrial circuits. Compared with Yan's pre-assignment RDL router[4] in total wirelength and CPU time, our proposed approach saves 3.7% of total wirelength and 27.0% of CPU time on the average.