T. Braun, O. Hölck, M. Voitel, Mattis Obst, S. Voges, K. Becker, R. Aschenbrenner, M. Schneider-Ramelow
{"title":"仔细看看扇形面板级包装","authors":"T. Braun, O. Hölck, M. Voitel, Mattis Obst, S. Voges, K. Becker, R. Aschenbrenner, M. Schneider-Ramelow","doi":"10.1109/EDTM55494.2023.10102969","DOIUrl":null,"url":null,"abstract":"Fan-out Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face-down have reached maturity and are introduced in high volume manufacturing. This paper discusses warpage in detail as one key challenge in fan-out packaging and how to influence the warpage during processing of a reconfigured panel for Chip first / RDL last approach.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Closer Look to Fan-out Panel Level Packaging\",\"authors\":\"T. Braun, O. Hölck, M. Voitel, Mattis Obst, S. Voges, K. Becker, R. Aschenbrenner, M. Schneider-Ramelow\",\"doi\":\"10.1109/EDTM55494.2023.10102969\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fan-out Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face-down have reached maturity and are introduced in high volume manufacturing. This paper discusses warpage in detail as one key challenge in fan-out packaging and how to influence the warpage during processing of a reconfigured panel for Chip first / RDL last approach.\",\"PeriodicalId\":418413,\"journal\":{\"name\":\"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-03-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTM55494.2023.10102969\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTM55494.2023.10102969","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fan-out Wafer and Panel Level Packaging are two of the dominating trends in microelectronics packaging. Both approaches with different flavors as RDL last face-up or face-down have reached maturity and are introduced in high volume manufacturing. This paper discusses warpage in detail as one key challenge in fan-out packaging and how to influence the warpage during processing of a reconfigured panel for Chip first / RDL last approach.
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