JPEG2000中高速EBCOT编码引擎的双符号编码算法编码器结构设计

2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI:10.1109/ICASIC.2005.1611315

Yizhen Zhang, Chao Xu, L. Chen

{"title":"JPEG2000中高速EBCOT编码引擎的双符号编码算法编码器结构设计","authors":"Yizhen Zhang, Chao Xu, L. Chen","doi":"10.1109/ICASIC.2005.1611315","DOIUrl":null,"url":null,"abstract":"This paper presents a flexible dual-symbol coding arithmetic coder (MQ coder) architecture design for the parallel coding engines of embedded block coding with optimization truncation (EBCOT) tier-1 in JPEG2000. The flexible MQ coder (FMQ) can encode two symbols simultaneously per clock cycle by using the optimized combination method. It increases the throughput rate of the arithmetic coding, which can match the high throughput rate of the parallel context modeling modules. Experimental results show that one FMQ are able to handle two bit-planes/data-pairs for the bit-plane parallel EBCOT coding engine, and the computation time is decreased about 24% compared with the engine by using the regular MQ coder","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A dual-symbol coding arithmetic coder architecture design for high speed EBCOT coding engine in JPEG2000\",\"authors\":\"Yizhen Zhang, Chao Xu, L. Chen\",\"doi\":\"10.1109/ICASIC.2005.1611315\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a flexible dual-symbol coding arithmetic coder (MQ coder) architecture design for the parallel coding engines of embedded block coding with optimization truncation (EBCOT) tier-1 in JPEG2000. The flexible MQ coder (FMQ) can encode two symbols simultaneously per clock cycle by using the optimized combination method. It increases the throughput rate of the arithmetic coding, which can match the high throughput rate of the parallel context modeling modules. Experimental results show that one FMQ are able to handle two bit-planes/data-pairs for the bit-plane parallel EBCOT coding engine, and the computation time is decreased about 24% compared with the engine by using the regular MQ coder\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611315\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611315","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 10

摘要

针对JPEG2000中具有优化截断(EBCOT)层的嵌入式分组编码并行编码引擎，提出了一种灵活的双符号编码算法编码器(MQ编码器)架构设计。灵活MQ编码器(FMQ)采用优化组合方法，可以在每个时钟周期内同时对两个符号进行编码。提高了算法编码的吞吐率，与并行上下文建模模块的高吞吐率相匹配。实验结果表明，对于位平面并行EBCOT编码引擎，一个FMQ可以处理两个位平面/数据对，与使用常规MQ编码器相比，计算时间减少了24%左右

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A dual-symbol coding arithmetic coder architecture design for high speed EBCOT coding engine in JPEG2000

This paper presents a flexible dual-symbol coding arithmetic coder (MQ coder) architecture design for the parallel coding engines of embedded block coding with optimization truncation (EBCOT) tier-1 in JPEG2000. The flexible MQ coder (FMQ) can encode two symbols simultaneously per clock cycle by using the optimized combination method. It increases the throughput rate of the arithmetic coding, which can match the high throughput rate of the parallel context modeling modules. Experimental results show that one FMQ are able to handle two bit-planes/data-pairs for the bit-plane parallel EBCOT coding engine, and the computation time is decreased about 24% compared with the engine by using the regular MQ coder

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2005 6th International Conference on ASIC

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