一种FPGA实现无线应用中ISI去除的高效均衡器

Chanpreet Kaur, R. Mehra
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引用次数: 10

摘要

在通信技术中,码间干扰(ISI)是由多径传播引起的。带宽有限的频率选择时间色散信道使传输信号失真,导致连续的符号模糊在一起。因此,设计发射机和接收机的主要目标是尽量减少码间干扰的影响,从而以尽可能小的错误率将数字数据传输到目的地。本文采用自适应均衡技术来对抗码间干扰。该模型采用ISE综合,Modelsim仿真,并在基于Virtex2的xc2v1500-5bg575目标设备上实现。结果表明,该模型具有使用简单且计算复杂度较低的LMS算法减少ISI的优点,并且在速度、成本和面积方面都比现有结果有所提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An FPGA implementation efficient equalizer for ISI removal in wireless applications
In telecommunication, Intersymbol interference (ISI) is caused by multipath propagation. The bandlimited frequency selective time dispersive channel distorts the transmitted signal, causing successive symbols to blur together. Therefore, the main objective of designing the transmitter and receiver is to minimize the effects of intersymbol interference, and thereby deliver the digital data to its destination with the smallest error rate possible. In this paper Adaptive Equalization technique is used to combat intersymbol interference. The proposed model is synthesized with ISE, simulated with Modelsim and implemented on Virtex2 based xc2v1500–5bg575 target device. The result shows that proposed model has the advantages of reduction in ISI using simple and less computational complex LMS algorithm along with enhanced performance in terms of speed, cost and area with existing results.
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