{"title":"一种新的超薄场效应管的器件温度降低方法","authors":"Minhyun Jin, S. Kim, Minkyu Song","doi":"10.1109/TENSYMP52854.2021.9550978","DOIUrl":null,"url":null,"abstract":"Conventionally, conductive material stacks composed of many metals and holes on silicon devices have kept excellent thermal paths which reduces junction temperature. However, according to the development of CMOS process technology, parasitic capacitance are also rapidly increasing and the thermal paths are also degrading. Thus, many ultra-thin FETs (Field Effect Transistor) are recently suffering from high temperature device problems. In this paper, device temperature reduction methodology with a new layout drawing technique is proposed for ultra-thin CMOS FETs. To verify the proposed new layout drawing technique, the secondary effects of various thermal paths with different metal stacks on junction temperature are analyzed, in terms of power consumption, oscillation frequency of ring oscillators, and etc. From the measured results of the oscillators, it is shown that the best heat-path design has about a 20%-lower change in junction temperature and a 1.5% higher oscillation frequency, compared to the conventional layouts. Furthermore, it is also shown that the proposed layout technique should be more effective with the ultra-thin FETs process rather than with the planar CMOS process.","PeriodicalId":137485,"journal":{"name":"2021 IEEE Region 10 Symposium (TENSYMP)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Device Temperature Reduction Methodology with a New Layout Drawing Technique for Ultra-thin FET\",\"authors\":\"Minhyun Jin, S. Kim, Minkyu Song\",\"doi\":\"10.1109/TENSYMP52854.2021.9550978\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Conventionally, conductive material stacks composed of many metals and holes on silicon devices have kept excellent thermal paths which reduces junction temperature. However, according to the development of CMOS process technology, parasitic capacitance are also rapidly increasing and the thermal paths are also degrading. Thus, many ultra-thin FETs (Field Effect Transistor) are recently suffering from high temperature device problems. In this paper, device temperature reduction methodology with a new layout drawing technique is proposed for ultra-thin CMOS FETs. To verify the proposed new layout drawing technique, the secondary effects of various thermal paths with different metal stacks on junction temperature are analyzed, in terms of power consumption, oscillation frequency of ring oscillators, and etc. From the measured results of the oscillators, it is shown that the best heat-path design has about a 20%-lower change in junction temperature and a 1.5% higher oscillation frequency, compared to the conventional layouts. Furthermore, it is also shown that the proposed layout technique should be more effective with the ultra-thin FETs process rather than with the planar CMOS process.\",\"PeriodicalId\":137485,\"journal\":{\"name\":\"2021 IEEE Region 10 Symposium (TENSYMP)\",\"volume\":\"71 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE Region 10 Symposium (TENSYMP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TENSYMP52854.2021.9550978\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE Region 10 Symposium (TENSYMP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TENSYMP52854.2021.9550978","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Device Temperature Reduction Methodology with a New Layout Drawing Technique for Ultra-thin FET
Conventionally, conductive material stacks composed of many metals and holes on silicon devices have kept excellent thermal paths which reduces junction temperature. However, according to the development of CMOS process technology, parasitic capacitance are also rapidly increasing and the thermal paths are also degrading. Thus, many ultra-thin FETs (Field Effect Transistor) are recently suffering from high temperature device problems. In this paper, device temperature reduction methodology with a new layout drawing technique is proposed for ultra-thin CMOS FETs. To verify the proposed new layout drawing technique, the secondary effects of various thermal paths with different metal stacks on junction temperature are analyzed, in terms of power consumption, oscillation frequency of ring oscillators, and etc. From the measured results of the oscillators, it is shown that the best heat-path design has about a 20%-lower change in junction temperature and a 1.5% higher oscillation frequency, compared to the conventional layouts. Furthermore, it is also shown that the proposed layout technique should be more effective with the ultra-thin FETs process rather than with the planar CMOS process.