5.5 GHz分频器封装的设计与优化

Huang Jinsheng, Zheng Hongyu, Gao Shang-tong
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引用次数: 0

摘要

高速ic封装要求高电性能、高I/O数、高互连密度、低热阻,特别是高电磁性能。随着工作频率的提高,与集成电路封装相关的寄生效应开始影响集成电路的性能。因此,有必要对包装的各种特性进行建模,以便更好地理解这些影响。包装设计和分析应借助计算机和一些CAD/CAA软件。本文以5.5GHz分频器封装为例,介绍了高速集成电路封装的设计与优化,包括模型、参数、仿真、分析和优化。最后给出了该封装的设计结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The design and optimization of a package for frequency divider at 5.5 GHz
High speed IC-packages require high electric performance, high I/O number, high interconnect density, low thermal resistance, especially high electromagnetic performance. The parasitics associated with integrated circuit packaging are beginning to affect the performance of the integrated circuit with the rise in operating frequencies. Hence it has become necessary to model various characteristics of the package to provide better understanding of these effects. The package design and analysis should be aided with computer and some CAD/CAA software. This paper introduces the design and optimization of the package for high speed IC, as an example, a package for 5.5GHz frequency divider, includes model, parameter, simulation, analysis and optimization. In the end, the design results of the package are given.
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