降低复杂性单核基于HEVC视频编解码器处理器的移动4K-UHD应用

2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin) Pub Date : 2016-09-01 DOI:10.1109/ICCE-Berlin.2016.7684727

Sukho Lee, Hyunmi Kim, N. Eum

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引用次数: 8

摘要

由于H.264对大尺寸超高清图像编码效率的限制，未来的视频编解码处理器必须在短时间内采用新标准化的高效视频编码(HEVC/H.265)。本文结合所设计的HEVC解码器和编码器，提出了一种低复杂度的HEVC视频编解码处理器。我们在今年使用三星28纳米CMOS工艺开发了这款编解码器处理器，这款低复杂度编解码器的尺寸保持在传统H.264/AVC芯片的范围内。该处理器采用简化的速率失真优化(RDO)和低功耗跳过模式，具有最优模式决策。与HM-13.0相比，编码器的bd速率损耗为35%，进入Skip模式时功耗低于250mW。该芯片及其内部SRAM大小分别为7.3 × 7.5mm2和300kB，当4K-UHD编码模式为30fps时，最大频率为600MHz。

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Reduced complexity single core based HEVC video codec processor for mobile 4K-UHD applications

A future video codec processor will have to adopt the newly standardized High Efficiency Video Coding (HEVC/H.265) in a short time due to the limit of H.264's coding efficiency for large sized UHD images. This paper combines our designed decoder and encoder for HEVC and proposes a low complexity HEVC video codec processor. We developed this codec processor with Samsung 28nm CMOS process in this year and the size of this low complexity codec keeps within the bounds of that of a conventional H.264/AVC chip. This single core based processor has an optimal mode decision with a simplified Rate Distortion Optimization (RDO) and a low power Skip mode. The encoder's BD-rate loss is 35% compared with HM-13.0 and the power consumption is below 250mW when entering the Skip mode. The chip and its internal SRAM size are 7.3 × 7.5mm2 and 300kB each and the maximum frequency is 600MHz when 4K-UHD encoding mode at 30 fps.

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2016 IEEE 6th International Conference on Consumer Electronics - Berlin (ICCE-Berlin)

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