{"title":"一种数字式校正集成adc增益误差的实用方法","authors":"Rongbin Hu, Yu Wen, Xiaoying Zhang","doi":"10.1109/IWECA.2014.6845545","DOIUrl":null,"url":null,"abstract":"A kind of practical method for digitally gain calibration of ADCs is proposed. The method is given in details as well as the architecture and circuit. The method has been successfully applied on a two-channel 8-bit time-interleaved ADC. Simulation shows that the gain of the 8-bit ADC can be adjusted with a step of 0.012dB and a full scale range of about 3dB. The measurement shows that the 8-bit ADC has a SNR of 37dB and 45dB before and after calibration, respectively.","PeriodicalId":383024,"journal":{"name":"2014 IEEE Workshop on Electronics, Computer and Applications","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A practical method for digitally calibrating gain error of integrated ADCs\",\"authors\":\"Rongbin Hu, Yu Wen, Xiaoying Zhang\",\"doi\":\"10.1109/IWECA.2014.6845545\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A kind of practical method for digitally gain calibration of ADCs is proposed. The method is given in details as well as the architecture and circuit. The method has been successfully applied on a two-channel 8-bit time-interleaved ADC. Simulation shows that the gain of the 8-bit ADC can be adjusted with a step of 0.012dB and a full scale range of about 3dB. The measurement shows that the 8-bit ADC has a SNR of 37dB and 45dB before and after calibration, respectively.\",\"PeriodicalId\":383024,\"journal\":{\"name\":\"2014 IEEE Workshop on Electronics, Computer and Applications\",\"volume\":\"57 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Workshop on Electronics, Computer and Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWECA.2014.6845545\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Workshop on Electronics, Computer and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWECA.2014.6845545","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A practical method for digitally calibrating gain error of integrated ADCs
A kind of practical method for digitally gain calibration of ADCs is proposed. The method is given in details as well as the architecture and circuit. The method has been successfully applied on a two-channel 8-bit time-interleaved ADC. Simulation shows that the gain of the 8-bit ADC can be adjusted with a step of 0.012dB and a full scale range of about 3dB. The measurement shows that the 8-bit ADC has a SNR of 37dB and 45dB before and after calibration, respectively.
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