基于自偏置多门控晶体管的高线性低噪声放大器

A. Abbasi, N. Sulaiman, R. Teymourzadeh
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引用次数: 3

摘要

噪声等级通常设定在最小信号的基本限制上。新的降噪技术和放大器电压噪声密度,但仍然提供高速度,高精度和低功耗的解决方案。低噪声放大器在射频技术中一直扮演着重要的角色。因此,本文提出了一种采用级联码自偏置多门控晶体管的高线性低噪声放大器。提出的系统覆盖0.9到2.4 GHz的应用。为了验证所提出的LNA作为射频技术瓶颈的功能,实现并合成了一个没有MGTR的级联LNA。并与单门LNA进行了比较。从综合结果来看,与增益为9 dB的单门LNA相比,本文提出的LNA获得了10 dBm的三阶输入截距点(IIP3)。所提出的LNA采用90 nm CMOS技术实现,IIP3为13 dBm, NF为1.9 dB,增益为9 dB, 2v电源功耗为7.9 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High linear low noise amplifier based on self-biasing multiple gated transistors
Noise level frequently set the basic limit on the smallest signal. New noise reduction technology and amplifiers voltage-noise density, yet still offer high speed, high accuracy and low power solution. Low noise amplifiers always play a significant role in RF technology. Hence in this paper, high linear low noise amplifier (LNA) using cascode self-biased multiple gated transistors (MGTR) is presented. The proposed system is covering 0.9 to 2.4 GHz applications. To verify the functionality of the proposed LNA as a bottleneck of RF technology, a cascode LNA without MGTR is implemented and synthesized. The comparison has been done with the single-gate LNA. From the synthesize result, proposed LNA obtained 10 dBm third-order input intercept point (IIP3) in compare with single-gate LNA at 9 dB gain. The proposed LNA is implemented in 90 nm CMOS technology and reported 13 dBm IIP3, 1.9 dB NF and 9 dB gain, while consuming 7.9 mW from 2 V supply.
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