S. Banerjia, A. Glaser, Christoforos Harvatis, S. Lipa, R. Pomerleau, T. Schaffer, A. Stanaski, Y. Tekmen, G. Bilbro, P. Franzon
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Issues in partitioning integrated circuits for MCM-D/flip-chip technology
In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning.
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