S. Banerjia, A. Glaser, Christoforos Harvatis, S. Lipa, R. Pomerleau, T. Schaffer, A. Stanaski, Y. Tekmen, G. Bilbro, P. Franzon
{"title":"用于MCM-D/倒装芯片技术的集成电路分区问题","authors":"S. Banerjia, A. Glaser, Christoforos Harvatis, S. Lipa, R. Pomerleau, T. Schaffer, A. Stanaski, Y. Tekmen, G. Bilbro, P. Franzon","doi":"10.1109/MCMC.1996.510787","DOIUrl":null,"url":null,"abstract":"In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning.","PeriodicalId":126969,"journal":{"name":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Issues in partitioning integrated circuits for MCM-D/flip-chip technology\",\"authors\":\"S. Banerjia, A. Glaser, Christoforos Harvatis, S. Lipa, R. Pomerleau, T. Schaffer, A. Stanaski, Y. Tekmen, G. Bilbro, P. Franzon\",\"doi\":\"10.1109/MCMC.1996.510787\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning.\",\"PeriodicalId\":126969,\"journal\":{\"name\":\"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-02-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1996.510787\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1996.510787","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Issues in partitioning integrated circuits for MCM-D/flip-chip technology
In order to successfully partition a high performance large monolithic chip onto MCM-D/flip-chip-solder-bump technology, a number of key issues must be addressed. These include the following: (1) Partitioning a single clock-cycle path across the chip boundary within using; (2) Ability to use off-the-shelf memories; (3) Using the MCM for power, ground, and clock distribution; and (4) Managing test costs. This paper presents a discussion on these issues, using a CPU as an example, and speculates on some interesting possibilities arising from partitioning.
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