为什么安装电感在配电网设计中很重要?

R. Fizesan, O. Pop, A. Taut
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引用次数: 1

摘要

减小配电网络中的噪声是电源完整性设计的关键步骤。主要工作是通过使用去耦电容将PDN阻抗保持在一定频率范围内的某一值,去耦电容可以在印刷电路板(PCB)级、封装或芯片中使用。尽管您可以使用任何类型的高频电容器获得相同的性能,但重要的是要考虑以牺牲大型外壳为代价的小型陶瓷外壳中的去耦电容器的效率。每个PCB设计人员都面临一定的限制,包括与仪表板、元件数量、需要布线的信号走线有关的限制,因此他将能够实现其目标,增加某些因素的影响,[16][20][21][22]。电容器与芯片及其过孔的接近程度,以及它的寄生(等效串联电感和等效串联电阻)决定了电容器对电流变化的反应速度。本文通过回答“为什么安装电感需要最小化以获得合适的配电网络(PDN)阻抗?”这个问题,回顾了最小化PDN噪声的可能解决方案。为了回答这个问题,将使用SPICE等效电路的PDN。这使得频率和瞬态响应都可以通过SPICE模拟完成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Why the mounting inductance is important in designing a Power Distribution Network?
Minimizing the noise in a Power Distribution Network (PDN) is a critical step in Power Integrity (PI) design. The main effort is to keep the PDN impedance under a certain value in a frequency range by using decoupling capacitors, which can be at Printed Circuit Board (PCB) level, in package or in chip. Although you can get the same performance with any type of capacitor for high frequencies, it is important to consider the efficiency of decoupling capacitors in small ceramic casings at the expense of the large enclosures. Each PCB designer faces certain restrictions, including those related to the gauge plate, number of components, signal traces that need to be routed, so he will be able to achieve its goal increasing the effect of certain factors, [16][20][21][22]. The proximity of the capacitor to the chip and to its vias, and also its parasitic (equivalent series inductance and equivalent series resistance) determine the speed at which the capacitor reacts to the change in current. This paper reviews possible solution to minimize the noise in a PDN by answering the question “Why the mounting inductance needs to be minimize in order to have a proper Power Distribution Network (PDN) impedance?”. To answer of this question, will be used a SPICE equivalent circuit of the PDN. This allows both frequency and transient response to be done with SPICE simulation.
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