N. Itoh, Y. Tsukamoto, Takeshi Shibagaki, K. Nii, H. Takata, H. Makino
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引用次数: 4
摘要
介绍了先进的矩形华勒斯树形施工方法。该方法实现了乘法器的紧凑布局和高速运行。利用该方法构造了一个32/spl倍/24位乘加器。采用0.15 um CMOS逻辑工艺技术和闪存实现了540 um/spl倍/840 um面积和300 MHz时钟速度。
A 32/spl times/24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure
We introduce the advanced rectangular styled Wallace-tree construction method. This method realizes a compact layout and high-speed operation of multiplier. A 32/spl times/24-bit multiplier-accumulator was constructed using this new method. 540 um/spl times/840 um area size and 300 MHz clock speed were achieved using 0.15 um CMOS logic process technology with flash memory.
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